Processing systems often utilize a cache hierarchy having multiple levels of caches available for access by one or more processor cores. For cache hierarchies with three or more cache levels, one of three caching policies is required in conventional processing systems with respect to data for an address cached at the highest-level cache (e.g., an L1 cache): (1) the data is not required to be copied or included in any other cache; (2) a copy of the data is required to always be included in the second-highest-level cache (e.g., the L2 cache), and upon eviction of the copy of the cached data from the second-highest-level cache, an invalidation message is sent to evict the cached data from the highest level cache as well; or (3) a copy of the data is required to always be included in the third-highest-level cache (e.g., the L3 cache), and upon eviction from the third-highest-level cache, an invalidation message is sent to evict the cached data from the highest-level cache as well. The first policy is problematic in that by not requiring a copy of cached data in any other cache level, the cached data may be inaccessible to a component that does not have access to that highest-level cache, or the cached data's absence from the lower-level caches may cause excessive cache misses before the cached data is found and accessed, thereby impacting system performance. The latter two policies are problematic in that they lead to excessive invalidation messaging and cache line evictions, which also negatively impact system performance.